A Risc Architecture Extended by an Efficient Tightly Coupled Reconfigurable Unit

In this paper, the architecture of an embedded processor extended with a tightly-coupled coarse-grain Reconfigurable Functional Unit (RFU) is proposed. The efficient integration of the RFU with the control unit and the datapath of the processor eliminate the communication overhead between them. To speed up execution, the RFU exploits Instruction Level Parallelism (ILP) and spatial computation. Also, the proposed integration of the RFU exploits efficiently the pipeline structure of the processor, leading to further performance improvements. Furthermore, a development framework for the introduced architecture is presented. The framework is fully automated, hiding all reconfigurable hardware related issues from the user. The hardware model of the architecture was synthesized in a 0.13um process and all information regarding area and delay were estimated and presented. A set of benchmarks is used to evaluate the architecture and the development framework. Experimental results prove performance improvements in addition with potential energy reduction.